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UNISONIC TECHNOLOGIES CO., LTD UR5596
DDR TERMINATION REGULATOR
DESCRIPTION
The UTC UR5596 is a linear bus termination regulator and designed to meet JEDEC SSTL-2(Stub-Series Terminated Logic) specifications for termination of DDR-SDRAM. It also can be used in SSTL-3 or HSTL (High-Speed Transceiver Logic) scheme. The device contains a high-speed OP AMP to provide excellent response to the load transients, and can deliver 1.5A continuous current and transient peaks up to 3A in the application as required for DDR-SDRAM termination. The UTC UR5596 also incorporates a VSENSE pin to provide superior load regulation and a VREF output as a reference for the chipset and DIMMs. Besides, an active low shutdown (SHDN) pin provides Suspend To RAM (STR) functionality. When SHDN is pulled low the VTT output will tri-state providing a high impedance output, but, VREF will remain active. A power savings advantage can be obtained in this mode through lower quiescent current. Regarding the output, VTT is capable of sinking and sourcing current while regulating the output voltage equal to VDDQ/2. The output stage has been designed to maintain excellent load regulation while preventing shoot through. The UTC UR5596 also incorporates two distinct power rails that separates the analog circuitry from the power output stage. This allows a split rail approach to be utilized to decrease internal power dissipation and permits UTC UR5596 to provide a termination solution for DDRII SDRAM.
CMOS IC
*Pb-free plating product number: UR5596L
FEATURES
* Source and sink current * Low output voltage offset * No external resistors required * Linear topology * Suspend To Ram (STR) functionality * Low external component count * Thermal shutdown protection
ORDERING INFORMATION
Ordering Number Normal Lead Free Plating UR5596-S08-R UR5596L-S08-R UR5596-S08-T UR5596L-S08-T UR5596L-S08-R (1) Packing Type (2) Package Type (3) Lead Plating (1) R: Tape Reel, T: Tube (2) S08: SOP-8 (3) L: Lead Free Plating, Blank: Pb/Sn Package SOP-8 SOP-8 Packing Tape Reel Tube
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UR5596
PIN CONFIGURATION
CMOS IC
PIN DESCRIPTION
PIN NO. 1 2 3 4 5 6 7 8 PIN NAME GND SHDN VSENSE VREF VDDQ AVIN PVIN VTT PIN FUNCTION Ground Shutdown Feedback pin for regulating VTT. Buffered internal reference voltage of VDDQ/2 Input for internal reference equal to VDDQ/2 Analog input pin Power input pin Output voltage for connection to termination resistors
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UR5596
BLOCK DIAGRAM
CMOS IC
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UR5596
ABSOLUTE MAXIMUM RATINGS
PARAMETER PVIN, AVIN, VDDQ to GND AVIN to GND(Note 1)
CMOS IC
SYMBOL RATINGS UNIT VDD -0.3 ~ +6 V Supply Voltage VDD 2.2 ~ 5.5 V Junction Temperature TJ +150 Operation Temperature TOPR 0 ~ +125 Storage Temperature TSTG -40 ~ +150 Note: Absolute maximum ratings are those values beyond which the device could be permanently damaged. Absolute maximum ratings are stress ratings only and functional device operation is not implied.
THERMAL DATA
PARAMETER Thermal Resistance Junction-Ambient SYMBOL JA RATINGS 150 UNIT /W
ELECTRICAL CHARACTERISTICS
(TJ=25C, VIN=AVIN=PVIN=2.5V, VDDQ=2.5V, unless otherwise specified). PARAMETER SYMBOL TEST CONDITIONS VIN = VDDQ = 2.3V VIN = VDDQ = 2.5V VREF Voltage VREF VIN = VDDQ = 2.7V VIN = VDDQ = 2.3V VIN = VDDQ = 2.5V IOUT = 0A VIN = VDDQ = 2.7V VTT Output Voltage VTT VIN = VDDQ = 2.3V VIN = VDDQ = 2.5V IOUT = 1.5A VIN = VDDQ = 2.7V High VIH Minimum Shutdown Level Low VIL VosTT IOUT = 0A IOUT = -1.5A VTT Output Voltage Offset (VREF - VTT) VTT IOUT = +1.5A Quiescent Current IQ IOUT = 0A Quiescent Current in Shutdown ISD SD = 0V Shutdown Leakage Current IQ_SD SD = 0V SD = 0V VTT Leakage Current in Shutdown IV VTT = 1.25V VSENSE Input Current ISENSE VREF Output Impedance ZVREF IREF = -30 ~ +30 A VDDQ Input Impedance ZVDDQ Thermal Shutdown TSD Thermal Shutdown Hysteresis TSD-HYS MIN 1.130 1.235 1.335 1.125 1.225 1.325 1.125 1.225 1.325 1.9 -20 -25 -25 TYP 1.158 1.258 1.358 1.159 1.259 1.359 1.159 1.259 1.359 MAX 1.185 1.285 1.385 1.190 1.290 1.390 1.190 1.290 1.390 0.8 20 25 25 500 150 5 10 UNIT V
V
V mV A A A A nA k k
0 0 0 320 115 2 1 13 2.5 100 165 10
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UR5596
PIN DESCRIPTIONS
AVIN , PVIN
CMOS IC
Input supply pins. AVIN is used to supply all the internal analog circuits and PVIN is used to provide the output stage to create VTT. These pins have the capability to work off separate supplies depending on the application. Higher voltages on PVIN will increase the maximum continuous output current because of output RDSON limitations at voltages close to VTT. But the internal power loss will also increase, thermally limiting the design. If the junction temperature exceeds the thermal shutdown than the part will enter a shutdown state identical to the manual shutdown where VTT is tri-stated and VREF remains active. For SSTL-2 applications, a good compromise would be to connect the AVIN and PVIN directly together at 2.5V. This eliminates the need for bypassing the two supply pins separately. The only limitation on input voltage selection is that PVIN must be equal to or lower than AVIN. It is recommended to connect PVIN to voltage rails equal to or less than 3.3V to prevent the thermal limit from tripping because of excessive internal power dissipation. VDDQ The input pin used to create the internal reference voltage from a resistor divider of two internal 50k resistors for regulating VTT and to guarantee VTT will track VDDQ/2 precisely. As a remote sense by connecting VDDQ directly to the 2.5V rail for SSTL-2 applications is an optimal implementation of VDDQ at the DIMM. This ensures that the reference voltage tracks the DDR memory rails precisely without a large voltage drop from the power lines. VSENSE The sense pin supply improved remote load regulation, if remote load regulation is not used then the VSENSE pin must still be connected to VTT. A long trace will cause a significant IR drop resulting in a termination voltage lower at one end of the bus than the other. Connect VSENSE pin to the middle of the bus to provide a better distribution across the entire termination bus then DDR performance will be improved. Take notice of when a long VSENSE trace is implemented in close proximity to the memory, noise pickup in the VSENSE trace can cause problems with precise regulation of VTT. A ceramic capacitor of 0.1uF is placed to next the VSENSE pin can help filter any high frequency signals and preventing errors. VREF VREF supply the buffered output of the internal reference voltage VDDQ/2. This output delivers the reference voltage for the Northbridge chipset and memory. Since these inputs are typically extremely high impedance, there should be little current drawn from VREF. A 0.1F~0.01F ceramic capacitor could be used to acquire better performance, located close to the pin to help with noise. This output remains active during the shutdown state and thermal shutdown events for the suspend to RAM functionality. VTT VTT is a regulated output for the bus resistors termination of DDR-SDRAM. It can track precisely the VDDQ/2 voltage with the sinking and sourcing current capability. The UTC UR5596 is designed to handle peak transient currents of up to 3A with a fast transient response. If a transient is expected to remain above the maximum continuous current rating for a significant amount of time then the output capacitor size should be large enough to prevent an excessive voltage drop. Although UTC UR5596 can handle large transient output currents, but it can not handling these for long durations since the limited thermal dissipation capability of SOP-8 package. If large currents are required for longer durations, then must ensure the maximum junction temperature is not exceeded, otherwise, the maximum output current will be degraded with heating. Proper thermal de-rating should always be used. While the temperature beyond the junction temperature, the thermal shutdown protection will be functioned, then VTT will tri-state until the part returns below the hysteretic trigger point.
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UR5596
CAPACITOR SELECTION
CMOS IC
A capacitor is recommended for improve performance during large load transients to prevent the input rail from dropping, even though UR5596 does not require for input stability. The input capacitor should be located as close as possible to the PVIN pin. The typical recommended value for AL electrolytic capacitors is 50 F and 10 F with X5R or better for Ceramic capacitors. If AVIN and PVIN are separated, the 47F capacitor should be placed as close to possible to the PVIN rail. An additional 0.1uF ceramic capacitor can be placed on the AVIN rail to prevent excessive noise from coupling into the device. UTC UR5596 has been designed to be insensitive of output capacitor size or ESR (Equivalent Series Resistance). The choice for output capacitor depends on the application and the requirements for load transient response of VTT. As a general recommendation the output capacitor should be sized above 100 F with a low ESR for SSTL applications with DDR-SDRAM. The value of ESR should be determined by the maximum current spikes expected and the extent at which the output voltage is allowed to droop.
THERMAL DISSIPATION
The UR5596 will generate heat result from internal power dissipation when current flow working. The device might be damaged any beyond maximum junction temperature rating. The maximum allowable internal temperature rise (TRmax) can be calculated given the maximum ambient temperature (TAmax) of the application and the maximum allowable junction temperature (TJmax). TRmax = TJmax - TAmax From this equation, the maximum power dissipation (PDmax) of the part can be calculated: PDmax = TRmax / JA The JA of UR5596 can be calculated (refer to JEDEC standard) and will depend on several package type, materials, ambient air temperature and so on.
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UR5596
TYPICAL APPLICATION CIRCUITS
CMOS IC
Following demonstrate several different application circuits to illustrate some of the options that are possible in configuring the UTC UR5596. The individual circuit performance can be found in the Typical Performance Characteristics that curve graphs illustrate how the maximum output current is affected by changes in AVIN and PVIN. STUB-SERIES TERMINATED LOGIC(SSTL) TERMINATION SCHEME SSTL was created to improve signal integrity of the data transmission across the memory bus. This termination scheme is essential to prevent data error from signal reflections while transmitting at high frequencies encountered with DDR-SDRAM. Class II single parallel termination(SSTL-2) is the most popular termination form. It involves one RS series resistor from the chipset to the memory and one RT termination resistor (refer to Figure 1). RS and RT are changeable to meet the current requirement from UR5596, the recommended values both RS and RT are 25
Figure 1. SSTL-Termination Scheme
FOR SSTL-2 APPLICATIONS For the majority of applications that implement the SSTL- 2 termination scheme, it is recommended to connect all the input rails to the 2.5V rail as Figure 2. This provides an optimal trade-off between power dissipation and component count and selection. UTC UR5596 SHDN VDDQ=2.5V VDD=2.5V SHDN VDDQ AVIN PVIN CIN + GND VSENSE VTT + COUT VTT=1.25V VREF VREF=1.25V CREF
+
Figure 2. Recommended SSTL-2 Implementation
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TYPICAL APPLICATION CIRCUITS(Cont.)
CMOS IC
Figure 3 illustrate another application that the power rails are split when power dissipation or efficiency are concerned. The output stage (PVIN) can be as lower as 1.8V, and the analog circuitry (AVIN) can be connected to a higher rail such as 2.5V, 3.3V or 5V. This allows the internal power dissipation to be lowered when sourcing current from VTT, but the disadvantage of this circuit is the maximum continuous current is reduced.
UTC UR5596 SHDN VDDQ=2.5V AVIN=2.2V ~ 5.5V PVIN=1.8V CIN + SHDN VDDQ AVIN PVIN GND VSENSE VTT + COUT VTT=1.25V VREF VREF=1.25V CREF
+
Figure 3. Lower Power Dissipation SSTL-2 Implementation
The third optional application is that PVIN connect to 3.3V and AVIN will be always limited to operation on the 3.3V or 5V to always equal or higher than PVIN. This configuration has the ability to provide the maximum continuous output current at the downside of higher thermal dissipation. The power dissipation increasing problem must be careful to prevent the junction temperature to exceed the maximum ranting. Because of this risk it is not recommended to supply the output stage with a voltage higher than a nominal 3.3V rail. UTC UR5596 SHDN VDDQ=2.5V AVIN=3.3V or 5.5V PVIN=3.3V CIN + SHDN VDDQ AVIN PVIN GND VSENSE VTT + COUT VTT=1.25V VREF VREF=1.25V CREF
+
Figure 4. SSTL-2 Implementation with higher voltage rails
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TYPICAL APPLICATION CIRCUITS(Cont.)
FOR DDR-II APPLICATIONS
CMOS IC
As a result of the separate VDDQ pin and an internal resistor divider, UR5596 can be utilized in DDR-II system, figure 5 and 6 show two recommended circuits in DDR-II SDRAM application. The output stage is connected to the 1.8V rail and the AVIN pin can be connected to either a 3.3V or 5V rail. If it is not desirable to use the 1.8V rail it is possible to connect the output stage to a 3.3V rail. The power dissipation increasing concern must be careful as well SSTL-II application. The advantage of configuration of figure 6 is that it has the ability to source and sink a higher maximum continuous current.
Figure 5. Recommended DDR-II Termination
UTC UR5596 SHDN VDDQ=1.8V AVIN=3.3V or 5.5V PVIN=3.3V CIN + SHDN VDDQ AVIN PVIN GND VSENSE VTT + COUT VTT=0.9V VREF VREF=0.9V CREF
+
Figure 6. DDR-II Termination with higher voltage rails
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TYPICAL CHARACTERISTICS
VIH and VIL 4 3.5 3 2.5 1.25 2 1.5 1 0.5 2 2.5 3 3.5 4 4.5 5 5.5 AVIN (V) 1.20 1.15 1.10 -30 1.40 1.35 1.30 VREF vs IREF
CMOS IC
-20
-10
0 IREF (
10 A)
20
30
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UR5596
TYPICAL CHARACTERISTICS(cont.)
CMOS IC
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UR5596
CMOS IC
UTC assumes no responsibility for equipment failures that result from using products at values that exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or other parameters) listed in products specifications of any and all UTC products described or contained herein. UTC products are not designed for use in life support appliances, devices or systems where malfunction of these products can be reasonably expected to result in personal injury. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice.
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